Peripheral Component Interconnect (PCI) Express is a third generation Input Output (3GIO) system that implements a serial, switched-packet, point-to-point communication standard at the system level. PCI Express has achieved many advantages over the prior shared bus system, such as quality of service (QoS), high speed peer-to-peer communication between external devices, adaptability, and low pin counts. The basic PCI Express architecture includes a root complex, a PCI Express switch chip, and various external devices. So far, PCI Express switching has only been implemented in a limited number of external devices.
One three-port PCI Express serial switch performs simultaneous comparisons of the target address value of an incoming data packet with the addresses of all possible directly-connected external devices. Since each external device's addressing is defined by a base address and a limit address, there are six comparisons performed for each port. A communication packet can arrive at any of the three ports, as many as 18 comparisons can be required to be performed in parallel within the PCI Express switch.
However, in recent years, as the speed of processors has increased and the size of processing systems has reduced in an unprecedented rate, the demand for more external devices has also increased. PCI Express serial switches will develop to accommodate more ports and thus more external devices. As port counts grow, though, the internal circuitry grows exponentially. A sixteen port switch, for example, can require 512 or more base and limit address comparisons for an incoming communication packet, using conventional switch architecture. Switches having 512 comparators to implement the comparisons are undesirable since comparators take up chip space, consume power, and increase latency of the system.
Thus, there is a need for a method and apparatus that will accommodate connection of a large number of external devices to a serial switch without using an exponentially increased number of comparators and registers and achieving high performance at the same time.